Intel Cyclone V Device FPGA part #5CGTFD9D5F27I7QS CMOS Image Sensor Gen Apollo

Gen Apollo

• Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex®-M3 Embedded Trace Macrocell™

SPI interface

• Fully compliant with DSL Forum TR-101 (Migration to Ethernet-based DSL Aggregation)

Intel Cyclone V Device FPGA part #5CGTFD9D5F27I7QS CMOS Image Sensor Gen ApolloLower power consumption: Built on TSMC's 28 nm low power (28LP) process technology and includes an abundance of hard intellectual property (IP) block, Up to 40% lower power consumption than the previous generation device. Improved logic integration and differentiation capabilities: 8 input adaptive logic module (ALM), Up to 13. 59 megabits (Mb) of embedded memory, Variable precision digital signal processing (DSP) blocks. Increased bandwidth capacity: